Xilinx Manuals & User Guides

Xilinx LogiCORE IP SRIO Gen2: Debugging and Packet Analysis Guide

Debugging Guide

A comprehensive guide from Xilinx detailing techniques for debugging issues with the LogiCORE IP Serial RapidIO Gen2 core, focusing on packet and signal analysis for hardware and simulation environments. The…

Xilinx KCU105 Evaluation Board User Guide

Guia d'usuari

Comprehensive user guide for the Xilinx KCU105 Kintex UltraScale FPGA evaluation board, detailing hardware features, setup, specifications, and system controller functions for FPGA development.

VCU1525 Reconfigurable Acceleration Platform User Guide

Guia d'usuari

This user guide provides detailed information on the Xilinx VCU1525 Reconfigurable Acceleration Platform, covering its features, specifications, installation, and deployment for data center applications like machine learning, data analytics, and…

Detalls de la interfície GEM TSU i compatibilitat amb IEEE 1588 per a Zynq UltraScale+

Especificació tècnica

Aquest document detalla el temps de connexió Gigabit Ethernet (GEM).amp Unit (TSU) interface and IEEE 1588 (Precision Time Protocol - PTP) support on Xilinx Zynq UltraScale+ devices. It covers clock source…

Xilinx KCU105 Evaluation Kit Quick Start Guide for Kintex UltraScale FPGA Development

Guia d'inici ràpid

A comprehensive quick start guide for the Xilinx KCU105 Evaluation Kit, featuring the Kintex UltraScale FPGA. Learn to set up the hardware, perform board self-tests, install the Vivado Design Suite,…

Guia de l'usuari del pla de control PCI Express TRD de KCU105

Guia d'usuari

This guide details the KCU105 PCI Express Control Plane Targeted Reference Design (TRD), covering its features, setup, operation, and modification. It targets the Kintex UltraScale XCKU040 FPGA and demonstrates PCIe…

Zynq UltraScale+ MPSoC Software Acceleration TRD User Guide

Guia d'usuari

User guide detailing the Zynq UltraScale+ MPSoC Software Acceleration Targeted Reference Design (TRD) for the ZCU102 evaluation platform. Explores features, hardware/software architecture, FFT computation flows, and performance comparisons.

Manual d'arquitectura Versal ACAP AIE-ML: una guia completa

especificació tècnica

Exploreu l'arquitectura Versal ACAP AIE-ML, detallant les seves tessel·les, memòria, interfícies i rendiment per a aplicacions avançades d'aprenentatge automàtic i processament de senyals.

XPHY I/O Source Synchronous Interfaces: A Guide to High-Speed I/O

nota d'aplicació

Explore the implementation of source synchronous high-speed I/O interfaces using Xilinx's Advanced I/O Wizard (AIOW) on Versal devices. This guide details single-bank and multi-bank designs, covering configuration, simulation, and best…

Getting Started with Xilinx Alveo Data Center Accelerator Cards

guia d'usuari

This user guide provides essential information for installing and setting up Xilinx Alveo Data Center Accelerator Cards, including hardware and software procedures for models like U200, U250, and U280. Learn…

Guia de l'usuari dels recursos SelectIO de l'arquitectura UltraScale

guia d'usuari

Aquesta guia de l'usuari detalla els recursos SelectIO dins de les arquitectures UltraScale i UltraScale+, que cobreixen els recursos d'interfície, els recursos lògics i les E/S d'alta densitat.

Guia de l'usuari de l'estimador de potència de Xilinx

Guia d'usuari

Details the Xilinx® Power Estimator (XPE) spreadsheet for power estimation. XPE assists with architecture evaluation and FPGA selection for specific design needs. XPE considers resource usage, toggle rates, and I/O…